1. Technical Field
The present invention relates to a semiconductor memory apparatus, and in particular, to an active cycle control circuit for a semiconductor memory apparatus.
2. Related Art
As shown in FIG. 1, an active cycle control circuit of a semiconductor memory apparatus according to the prior art includes a precharge signal output unit 10 that outputs a precharge signal pcg according to a ready signal ready, a ready signal output unit 20 that outputs the ready signal ready and a delayed ready signal ready_d according to an address transition signal atdsum and a ready reset signal ready_reset, a refresh standby signal output unit 30 that outputs a refresh standby signal ref_standby according to a refresh request signal srefreq and a refresh active signal rowact_ref that activates a word line for refresh, and an active control unit 40 that outputs the refresh active signal rowact_ref, the ready reset signal ready_reset, and a row active signal rowact that activates a word line so as to perform an external command (read or write) according to the precharge signal pcg, the delayed ready signal ready_d, and the refresh standby signal ref_standby.
The operation of the active cycle control circuit according to the prior art having the above-described structure will be described with reference to FIGS. 1 and 2.
First, a word line active operation for performing the external command, for example, a ‘read’ command, will be described.
When an address is changed according to the read command, the address transition signal atdsum is enabled to a logic high level.
Accordingly, the ready signal output unit 20 enables the ready signal ready to a logic high level and then enables the delayed ready signal ready_d to a logic high level after a predetermined delay time lapses.
When the ready signal ready is enabled at the logic high level, the precharge signal output unit 10 enables the precharge signal pcg to the logic high level.
If the refresh standby signal ref_standby is disabled to a logic low level at a time when the precharge signal pcg is enabled at the logic high level, the active control unit 40 enables the row active signal rowact to the logic high level.
A word line corresponding to the changed address is activated according to the row active signal rowact, and then a read operation is performed. The word line is activated until the address is changed again.
If the delayed ready signal ready_d is enabled at the logic high level, the active control unit 40 enables the ready reset signal ready_reset to the high level.
As the ready reset signal ready_reset is enabled at a logic high level, the ready signal output unit 20 resets the ready signal ready in a the logic low level and prepares a next read cycle.
Next, a word line active operation for performing a refresh operation will be described.
The refresh request signal srefreq is generated at every prescribed refresh cycle.
If the refresh request signal srefreq is enabled, the refresh standby signal output unit 30 enables the refresh standby signal ref_standby to the logic high level.
In a state where the refresh standby signal ref_standby is enabled at the logic high level, if the precharge signal pcg is enabled and then a precharge operation is performed, the active control unit 40 needs to enable the refresh active signal rowact_ref to the logic high level such that the corresponding word line is activated and the refresh operation is performed.
However, as shown in FIG. 2, even though the refresh standby signal ref_standby is enabled at high level according to the refresh request signal srefreq, when the read cycle is proceeding, the refresh operation is not performed. Then, when a new address is input after a read cycle time tRC, the refresh active signal rowact_ref is enabled to the logic high level, such that the refresh operation is performed and then the read operation is performed.
As described above, if the read cycle time tRC of the known semiconductor memory apparatus becomes longer than a refresh cycle tREF, the refresh operation is performed during a cycle of the read cycle time tRC.
In order to preserve data values stored in cells of the semiconductor memory apparatus, the refresh operation needs to be repeatedly performed according to the prescribed refresh cycle tREF.
However, when the refresh operation is not performed at every refresh cycle tREF, the data stored in the cells may be lost. Accordingly, in the prior art, in order to prevent data loss, a method that limits a maximum value of the read cycle time tRC is used.
As such, in the semiconductor memory apparatus according to the prior art, the maximum value of the read cycle time tRC is limited in order to perform the refresh operation cyclically. However, there are many cases where, in a system using the above-described method, a read cycle time larger than the maximum value is required, whereby the above-described method cannot be used.